1. Field of the Invention
The specification, the drawings, and the claims of the present invention (hereinafter referred to as “this specification and the like”) disclose a logic circuit, a retention circuit, a storage circuit, a processing unit, another semiconductor device, a driving method thereof, a manufacturing method thereof, and the like. The technical field of one embodiment of the present invention is not limited to the above technical field. For example, one embodiment of the present invention relates to an imaging device, a display device, a light-emitting device, an electric storage device, a driving method thereof, or a manufacturing method thereof.
2. Description of the Related Art
The reduction in power consumption of electronic devices has been highly required. Thus, the reduction in power consumption of integrated circuits (IC) such as CPUs is a major challenge in circuit design. The power consumption of ICs is broadly classified into operating power consumption (dynamic power) and non-operating (standby) power consumption (static power). Dynamic power increases when operating frequency increases for high performance. Static power is power consumed mostly by the leakage current of transistors. Examples of leakage current include subthreshold leakage current, gate tunnel leakage current, gate-induced drain leakage (GIDL) current, and junction tunnel leakage current. These leakage currents increase in accordance with scaling down of transistors. The increase in demand for reduction in power consumption of ICs is a large barrier to high performance and high integration. Thus, a technique for achieving both the reduction in power consumption and high performance or high integration has been considered.
In order to reduce the power consumption of a semiconductor device, circuits that do not need to operate are stopped by power gating or clock gating. A flip-flop (FF) is a logic circuit included a lot in a semiconductor device that stores data temporarily. Thus, the reduction in power consumption of the FF leads to the reduction in power consumption of a semiconductor device including the FF. When a general FF is powered off, data retained therein is lost.
For example, Non-Patent Document 1 discloses an FF with a smaller number of transistors operated by clock signals. Dynamic power that is consumed by input of clock signals is reduced. For example, in Non-Patent Document 2, a ferroelectric memory-based nonvolatile logic circuit for data backup of the FF is provided to perform power gating. Standby leakage current can be made almost zero when power supply is stopped by power gating.
By taking advantage of extremely low off-state current of a transistor whose active layer is formed using an oxide semiconductor (hereinafter, such a transistor may be referred to as an oxide semiconductor transistor or an OS transistor), a retention circuit capable of retaining data even when powered off has been proposed. Non-Patent Document 3 discloses power gating of a processor by using a retention circuit that includes an OS transistor for each of an FF and an SRAM, for example.